FPGA-Based Hardware Accelerator for Matrix Inversion

Matrix inversion is a computationally expensive operation in many scientific applications. Performing matrix inversion of rank deficient large order matrices is still a challenge due to its computational overhead. This paper presents the hardware implementation of matrix inversion with (i) singular value decomposition (SVD) based on Lanczos and implicit triQR algorithms, (ii) QR method that uses modified Gram–Schmidt (MGS) technique and (iii) inbuilt linear algebra package QR inverse using Xilinx Vivado high level synthesis platform. All the three algorithms are implemented on Pynq-Z1 Field Programmable Gate Array (FPGA) using System on Chip (SoC) approach. The resource utilization along with accuracy, hardware execution time with and without loop optimization are reported for the aforementioned matrix inversion techniques of different matrix sizes. We achieved the hardware acceleration factor with loop optimization as 111x and 104x, respectively, for the matrix inversion of the MGS algorithm and SVD based on Lanczos algorithm with respect to the software implementation execution time on Pynq-Z1 FPGA for the matrix size 90 × 90. © 2022, The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd.