Design of Ternary Logic Circuits Using GNRFET and RRAM

In this paper, the designs of ternary digital circuits are discussed. The ternary logic is a better choice over conventional logics due its extraordinary offers such as high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented in this paper to design the ternary circuits using graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The dimer line of graphene nanoribbon (GNR) is used to control the threshold voltage of GNRFETs. The RRAM is used because it has multilevel cell capacity that enables the multiple resistance state storage in a single cell. The ternary logic basic circuits such as standard ternary inverter (STI), NAND and NOR circuits are proposed. In addition, ternary half adder circuit is designed that helps to develop the complex circuits. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). Furthermore, the obtained circuit performances are compared with carbon nanotube FETs (CNTFETs)-based and RRAM-based circuits. The comparison results show that the proposed GNRFET and RRAM circuits achieved 46.11% of overall performance improvement over the CNTFET and RRAM circuits. Furthermore, line edge roughness (Pr) effect on the proposed STI and half adder circuit performance is investigated. The delay values are increased, and the power and PDP values are decreased for the higher Pr values. The effect of process, voltage and temperature (PVT) variations on proposed STI and half adder circuits is also performed to analyze the performance. It noticed that the proposed STI and half adder circuits show minimum variation on performance for the PVT variations.