Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers

We studied filtered-x least-mean-square (FxLMS) and filtered-s LMS (FsLMS) algorithms and observed that air–electrical interface of active noise controller (ANC) introduces delay in the error calculation, and that could make the hardware structure inefficient. In this paper, we propose delayed FxLMS (DFxLMS) and delayed FsLMS (DFsLMS) algorithm to address this issue. We have presented the performance of DFxLMS and DFsLMS algorithms through simulation study and found negligible performance degradation over FxLMS and FsLMS algorithms for one-sample delay, but severe performance degradation for two or higher sample delays. Based on these finding, we have chosen DFxLMS and DFsLMS algorithms instead of FxLMS and FsLMS to perform controller output computation and error computation concurrently in two separate pipeline stage. Block formulation of DFxLMX and DFsLMS also presented and parallel structures are derived to further explore efficiency of hardware structures. We have derived folded structures of DFsLMS- and delayed block FsLMS (DBFsLMS)-based single-channel ANC, and DBFsLMS-based dual-channel ANC for low-complexity realization by resource sharing. Theoretical estimate demonstrate that the DBFxLMS and DBFsLMS structures offer nearly L times higher throughput than the DFxLMS and DFsLMS structures and involve proportionately less hardware resource as register complexity of block-based structures is independent of block size (L). Compared with the existing FxLMS-based structure, the DBFxLMS structure involves L times more multipliers and adders, (3Q+2)\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$(3Q+2)$$\end{document} less registers and offers more than L times higher throughput, where Q is the secondary-path filter length. ASIC synthesis result shows that the DBFxLMS and DBFsLMS structures involve 11 % and 24 % less area-delay product (ADP), and 20 % and 30 % less energy per sample (EPS) than the DFxLMS and DFsLMS structures, respectively. The proposed DFxLMS and DBFxLMS structures involve 55 % and 58 % less ADP, 30 % and 41 % less EPS than those of the existing FxLMS-based structure and offers significantly higher throughput. Since the current design trend with increasing transistor density moves toward higher level of parallelism in implementation to reduce computation time and energy consumption, the proposed design approach would be interesting and useful for low-power implementation of ANC.