Blood vessel segmentation from high-resolution fundus images is a necessary step in several retinal pathologies detection. Automatic blood vessel segmentation is a computing-intensive task, which raises the need for acceleration with hardware architectures. In this paper, we propose two architectures for blood vessel segmentation using a matched filter (MF). The first architecture is a scalable hardware architecture, while the second one is an application-specific instruction-set processor. An efficient, real-time hardware implementation of the algorithm is made possible through parallel processing and efficient resource sharing. A tool for the automatic generation of particularized HDL descriptions of the architecture is proposed. The tool starts from a common architecture template and takes as input the parameters of the MF. A designer thus gains a significant amount of flexibility and productivity with the parameter selection problem and the evaluation of corresponding implementations. Several designs were verified and implemented on an FPGA platform. Performance in terms of area utilization and maximum frequency are reported. The results show significant improvement over state-of-the-art implementations, by up to a factor of 14× for high-resolution fundus images. The second architecture is based on the Tensilica Xtensa LX processor. With only two additional custom instructions requiring an additional 4× the area of the basic processor, the ASIP achieves a significant speedup of 7.76× when compared to the basic processor, while retaining all its flexibility.
