Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

被引：0
|
作者：
Paolo Rossi
Francesco Svelto
Andrea Mazzanti
Pietro Andreani
机构：
[1] Università di Pavia,Dipartimento di Elettronica
[2] Università di Modena e Reggio Emilia,Dipartimento di Ingegneria dell’Informazione
[3] Technical University of Denmark,Center for Physical Electronics, Ørsted.DTU
来源：
Analog Integrated Circuits and Signal Processing | 2004年 / 42卷 / 1期
关键词：
Noise Figure; CMOS Technology; CMOS Process; Minimum Noise; Theoretical Minimum;
D O I：
10.1007/s10470-004-6845-z
中图分类号：
学科分类号：
摘要：
Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.
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页码：31 / 36
页数：5
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