Continuous-time delta-sigma modulator using vector filter in feedback path to reduce effect of clock jitter and excess loop delay

被引：0

作者：

Yuki Kimura

Akira Yasuda

Michitaka Yoshino

机构：

[1] University of Hosei,Engineering Research Course

[2] University of Hosei,Faculty of Science and Engineering

来源：

Analog Integrated Circuits and Signal Processing | 2013年 / 75卷

关键词：

Analog-to-digital converter (ADC); Continuous-time delta-sigma modulator (CTDSM); Vector filter; Clock jitter; Excess loop delay;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper, we propose a novel delta-sigma modulator (DSM) that reduces the effects of clock jitter and excess loop delay by using a vector filter in the feedback path. The vector filter divides the input signal into a high-frequency part and a low-frequency part. The low-pass signal is placed in the path to the first-stage digital-to-analog converter for reducing the effects of the clock jitter, and the high-pass signal is placed in the feedback path to the last integrator in order to compensate for the excess loop delay. The DSM using the vector filter in the feedback path (DSM-VF) is verified using MATLAB/Simulink. Further, a clock jitter (0.1 %) in DSM-VF leads to an improvement in the signal-to-noise-ratio (SNR) to 22.5 dB as compared to the SNR of a conventional CTDSM. Moreover, the SNR deterioration caused by the excess loop delay is improved.

引用

页码：279 / 286

页数：7