Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine

The goal of this research is to enable the actual building of parallel machines. The example chosen in this paper is a heterogeneous parallel machine with an intrinsic asynchronous behavior. An asynchronous router fully supports such a logical asynchronism. However, every parallel processor would exhibit asynchronism similar enough to warrant the study of a general methodology. The main part of the paper deals with an original method that ensures a hazard-free self-timed design assuming the worst conditions for robustness. Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminated by an optimal covering. A new variable labelled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of the above-mentioned router. Peculiar fully customized cells were designed. Circuit-measured performances as well as some machine inner-communication performances are presented.