LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

被引：0
|
作者：
Simon C. Li
机构：
[1] University of Science and Technology,Advanced Technology & Integrated System Laboratory (ATIS Lab.), Department of Humanity & Science, National Yunlin
来源：
Analog Integrated Circuits and Signal Processing | 2002年 / 33卷
关键词：
analog multiplier; modified bridged-triode scheme (MBTS);
D O I：
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中图分类号：
学科分类号：
摘要：
A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good linearity, lower voltage operation/power consumption, less total harmonic distortions (THD) and wider frequency response. The fabricated chip in TSMC 0.35 μm n-well SPQM CMOS technology has a nonlinearity error less than 42 dB over ±0.5 V input range under a nominal supply voltage of ±1.5 V,and consumes the total power dissipation of 2.7 mW.
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页码：43 / 56
页数：13
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