Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation

被引：0
作者：
Tika Ram Pokhrel
Jyoti Kandpal
Alak Majumder
机构：
[1] National Institute of Technology Arunachal Pradesh,Integrated Circuit & System Lab, Department of ECE
[2] Graphic Era Hill University,undefined
来源：
Silicon | 2023年 / 15卷
关键词：
Full adder; Hybrid full adder; Junctionless transistor; Strained silicon; Work function modulation;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The impact of the work function modulation (WFM) in sub-20nm strained silicon channel double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power arithmetic circuit applications. A 14nm double gate junctionless transistor (DGJLT) followed by formation of strained channel and WFM in metal gate is designed on sentaurus TCAD, where 2-D mixed mode simulation at supply voltage (VDD) = 0.8V is performed to configure a hybrid full adder (HFA). From the analyses, the WFM based HFA is found to be superior by providing the least power, delay and PDP. The variability of HFAs is also tested as a function of the physical parameters like VDD, load capacitor, and temperature.
引用
收藏
页码：4513 / 4519
页数：6
相关论文
共 111 条
[1]  
Bui HT(2002)Design and analysis of low-power 10-transistor full adders using novel xor-xnor gates IEEE Trans Circ Syst II: Analog and Digit Signal Process 49 25-30
[2]  
Wang Y(1992)Low-power cmos digital design IEICE Trans Electron 75 371-382
[3]  
Jiang Y(2005)A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits IEEE Trans Very Large Scale Integr (VLSI) Syst 13 686-695
[4]  
Chandrakasan AP(2012)Surface-potential-based drain current model for long-channel junctionless double-gate mosfets IEEE Trans Electron Devices 59 3292-3298
[5]  
Sheng S(2010)Nanowire transistors without junctions Nature Nanotechnol 5 225-229
[6]  
Brodersen RW(2011)A full-range drain current model for double-gate junctionless transistors IEEE Trans Electron Devices 58 4219-4225
[7]  
Chang CH(2011)Simple analytical bulk current model for long-channel double-gate junctionless transistors IEEE Electron Device Lett 32 704-706
[8]  
Gu J(2002)On the enhanced electron mobility in strained-silicon inversion layers J Appl Phys 92 7320-7324
[9]  
Zhang M(2006)Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-cmos logic style IEEE Trans Very Large Scale Integr (VLSI) Syst 14 1309-1321
[10]  
Chen Z(2011)Bulk planar junctionless transistor (bpjlt): an attractive device alternative for scaling IEEE Electron Device Lett 32 261-263
12345678910