FPGA-based acceleration of Davidon-Fletcher-Powell quasi-Newton optimization method

被引：10

作者：

Liu Q. ^{[1
]}

Sang R. ^{[1
]}

Zhang Q. ^{[1
,2
]}

机构：

[1] School of Electronic Information Engineering, Tianjin University, Tianjin

[2] Department of Electronics, Carleton University, Ottawa

来源：

Transactions of Tianjin University | 2016年 / 22卷 / 05期

关键词：

field programmable gate array; hardware acceleration; quasi-Newton method;

D O I：

10.1007/s12209-016-2870-0

中图分类号：

学科分类号：

摘要：

Quasi-Newton methods are the most widely used methods to find local maxima and minima of functions in various engineering practices. However, they involve a large amount of matrix and vector operations, which are computationally intensive and require a long processing time. Recently, with the increasing density and arithmetic cores, field programmable gate array (FPGA) has become an attractive alternative to the acceleration of scientific computation. This paper aims to accelerate Davidon-Fletcher-Powell quasi-Newton (DFP-QN) method by proposing a customized and pipelined hardware implementation on FPGAs. Experimental results demonstrate that compared with a software implementation, a speed-up of up to 17 times can be achieved by the proposed hardware implementation. © 2016, Tianjin University and Springer-Verlag Berlin Heidelberg.

引用

页码：381 / 387

页数：6

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