This research investigates the virtually doped dual gate junctionless impact ionization MOS (DG-JL-IMOS). Virtually doped source and drain regions are realized through the genesis of charge plasma using different work-functions for their electrodes, easing the process complexity with simultaneous reduction of process-induced variations to implant uniform doping. The proposed DG-JL-IMOS device exhibits two order increase in ION/IOFF\documentclass[12pt]{minimal}
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\begin{document}$$I_{ON}/I_{OFF}$$\end{document} ratio at a lower source bias of -4.5\documentclass[12pt]{minimal}
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\begin{document}$$-4.5$$\end{document}V with respect to -5\documentclass[12pt]{minimal}
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\begin{document}$$-5$$\end{document}V required for a single gate JIMOS device. This work further examines the breakdown behavior of the proposed DG-JL-IMOS by analyzing carrier density distribution, impact ionization, and electric field profile through extensive TCAD simulations. The proposed device exhibits a super steep sub-threshold swing (SS) of 0.6 mV/dec over several orders of drain current, which is not achieved by any other counterpart steep-slope technologies. The effect of interface traps on the proposed DG-JL-IMOS is studied and investigated for hysteresis in the transfer characteristics. Furthermore, analog parameters such as transconductance (gm\documentclass[12pt]{minimal}
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\begin{document}$$g_{m}$$\end{document}), unity gain cutoff-frequency (fT\documentclass[12pt]{minimal}
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\begin{document}$$f_{T}$$\end{document}), and current gain of the proposed device are evaluated and compared with conventional DG-IMOS. It is observed that the proposed device shows a 2.6×\documentclass[12pt]{minimal}
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\begin{document}$$2.6\times $$\end{document} increase in ION\documentclass[12pt]{minimal}
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\begin{document}$$1.7\times $$\end{document} higher gm\documentclass[12pt]{minimal}
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\begin{document}$$1.6\times $$\end{document} higher fT\documentclass[12pt]{minimal}
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\begin{document}$$f_{T}$$\end{document}, and a 5 dB improvement in current gain compared to conventional DG-IMOS. The proposed DG-JL-IMOS device breakdowns at a voltage, (VBD\documentclass[12pt]{minimal}
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\begin{document}$$V_{BD}$$\end{document}) of -4.21\documentclass[12pt]{minimal}
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\begin{document}$$-4.21$$\end{document}V, whereas DG-IMOS breakdowns at -4.75\documentclass[12pt]{minimal}
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\begin{document}$$-4.75$$\end{document}V. The enhanced performance metrics of DG-JL-IMOS elucidate its suitability for high-speed and high-performance analog applications.