Above Gbit/s data transmission using full-parallel block turbo decoder architectureArchitecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s

被引:0
作者
Christophe Jego
Patrick Adde
Camille Leroux
机构
[1] Technopôle Brest-Iroise,GET/ENST Bretagne, CNRS TAMCIC UMR 2872
来源
Annales Des Télécommunications | 2007年 / 62卷 / 1-2期
关键词
Transmission numérique; Haut débit; Code correcteur erreur; Turbocode; Architecture parallèle; Décodeur; Digital transmission; High rate; Error correcting code; Turbo code; Parallel architecture; Decoder;
D O I
10.1007/BF03253257
中图分类号
学科分类号
摘要
This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory block between each half-iteration to be removed. In fact, the proposed architecture opens the way to numerous applications such as optical transmission. In particular, our block turbo decoding architecture can support optical transmission at data rates above Gbit/s
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页码:214 / 239
页数:25
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