A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

被引:0
作者
Rami Ahola
Jyrki Vikla
Saska Lindfors
Jarkko Routama
Kari Halonen
机构
[1] Helsinki University of Technology,Electronic Circuit Design Laboratory
来源
Analog Integrated Circuits and Signal Processing | 1999年 / 18卷
关键词
frequency synthesis; phase-locked loop; radio frequency; voltage-controlled oscillator;
D O I
暂无
中图分类号
学科分类号
摘要
This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 μm BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.
引用
收藏
页码:43 / 54
页数:11
相关论文
共 17 条
[1]  
Rudell J. C.(1997)A 1.9 GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless Telephone Applications IEEE Journal of Solid State Circuits 32 2071-2088
[2]  
Ou J.(1994)A Sub-1 mA 1.5-GHz Silicon Bipolar Dual Modulus Prescaler IEEE Journal of Solid-State Circuits 29 1206-1211
[3]  
Cho T. B.(1995)A 2.7–4.5V Single Chip GSM Transceiver RF Integrated Circuit IEEE Journal of Solid State Circuits 30 1421-1429
[4]  
Chien G.(1990)A New Low-Noise 100 MHz Balanced Relaxation Oscillator IEEE Journal of Solid-State Circuits 25 692-698
[5]  
Brianti F.(undefined)undefined undefined undefined undefined-undefined
[6]  
Weldon J. A.(undefined)undefined undefined undefined undefined-undefined
[7]  
Gray P. R.(undefined)undefined undefined undefined undefined-undefined
[8]  
Seneff T.(undefined)undefined undefined undefined undefined-undefined
[9]  
McKay L.(undefined)undefined undefined undefined undefined-undefined
[10]  
Sakamoto K.(undefined)undefined undefined undefined undefined-undefined