In-memory computing with emerging nonvolatile memory devices

被引:0
作者
Caidie Cheng
Pek Jun Tiw
Yimao Cai
Xiaoqin Yan
Yuchao Yang
Ru Huang
机构
[1] University of Science and Technology Beijing,State Key Laboratory for Advanced Metals and Materials, School of Materials Science and Engineering
[2] Peking University,Key Laboratory of Microelectronic Devices and Circuits (MOE), Department of Micro/nanoelectronics
[3] Peking University,Center for Brain Inspired Chips, Institute for Artificial Intelligence
[4] Chinese Institute for Brain Research (CIBR),Center for Brain Inspired Intelligence
[5] Beijing,undefined
来源
Science China Information Sciences | 2021年 / 64卷
关键词
in-memory computing; von Neumann bottleneck; nonvolatile memory; energy efficiency; neural network;
D O I
暂无
中图分类号
学科分类号
摘要
The von Neumann bottleneck and memory wall have posed fundamental limitations in latency and energy consumption of modern computers based on von Neumann architecture. In-memory computing represents a radical shift in the computer architecture that can address such problems by merging computing functions within the memory itself. In this article, we review the emerging nonvolatile memory devices, such as resistance-based and charge-based memory devices, that are explored for in-memory computing applications. We will provide an overview of the materials, mechanisms, and integration of these devices, and discuss the optimizations at the device and array levels that are required to better support in-memory computing. Recent progress in the application of in-memory computing in artificial neural networks, spiking neural networks, digital logic in memory as well as hardware security will also be discussed. Finally, we will discuss the remaining challenges in this field and potential pathways to address them.
引用
收藏
相关论文
共 564 条
[1]  
Wulf W A(1995)Hitting the memory wall: implications of the obvious ACM SIGARCH Comput Archit News 23 20-24
[2]  
McKee S A(1978)Can programming be liberated from the von Neumann style? Commun ACM 21 613-641
[3]  
Backus J(2014)A million spiking-neuron integrated circuit with a scalable communication network and interface Science 345 668-673
[4]  
Merolla P A(2016)The chips are down for Moore’s law Nature 530 144-147
[5]  
Arthur J V(2019)Processing data where it makes sense: enabling in-memory computation Microprocessors MicroSyst 67 28-41
[6]  
Alvarez-Icaza R(1994)The uniform memory hierarchy model of computation Algorithmica 12 72-109
[7]  
Waldrop M M(2011)GPUs and the future of parallel computing IEEE Micro 31 7-17
[8]  
Mutlu O(2017)Efficient processing of deep neural networks: a tutorial and survey Proc IEEE 105 2295-2329
[9]  
Ghose S(1997)A case for intelligent RAM IEEE Micro 17 34-44
[10]  
Gómez-Luna J(2020)Memory devices and applications for in-memory computing Nat Nanotech 15 529-544