Cache modeling and optimization for portable devices running MPEG-4 video decoder

There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is an important and demanding multimedia application. To satisfy the growing consumer demands, more functions are added to support MPEG-4 video applications. With improved CPU speed, memory sub-system deficiency is the major barrier to improving the system performance. Studies show that there is sufficient reuse of values for caching that significantly reduce the memory bandwidth requirement for video data. Software decoding of MPEG-4 video data generates much more cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is cache modeling and optimization for portable communication devices running MPEG-4 video decoding algorithm. The architecture we simulate includes a digital signal processor (DSP) for running the MPEG-4 decoding algorithm and a memory system with two levels of caches. We use VisualSim and Cachegrind simulation tools to optimize cache sizes, levels of associativity, and cache levels for a portable device decoding MPEG-4 video.