OptiPlace: optimized placement solution for mixed-size designs

被引:0
作者
Prasun Datta
Shyamapada Mukherjee
机构
[1] National Institute of Technology,
来源
Analog Integrated Circuits and Signal Processing | 2021年 / 109卷
关键词
Physical design automation; Placement; Mixed-size design; Routability; Routing congestion; Scaled wirelength; Pin density;
D O I
暂无
中图分类号
学科分类号
摘要
In this paper, an optimized placement approach has been presented for mixed-size designs. A novel initial placement approach is introduced to achieve routability-aware global placement using new routability-aware cell clustering, cluster positioning, cluster movement, and pin offset based cell spreading methods. The routability-aware cell clustering groups a set of cells to lookahead the circuit routability. A new cell spreading methodology is employed based on the pin offsets to keep control on total wirelength. A routability-aware legalization has been implemented using new circle rolling and block sliding techniques. Finally, a routability-aware detailed placement is used to refine the placement in order to yield an optimized placement in terms of wirelength and routability for mixed-size designs. The detailed placement implemented by novel congestion hot spot detection, congestion contributing cells identification, congestion contributing cell movement techniques. A routing-congestion reduction method is used in detailed placement phase to refine the placement solution to achieve better routability. Our proposed placer is experimentally tested on ICCAD 2012 contest benchmarks. The solution quality of this proposed approach achieves improvised results than the contemporary in terms of HPWL, scaled wirelength, and routability. It achieves 1.02% and 3.53% improvement in terms of HPWL and routing congestion over one of the recent placers Ripple 2.0.
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收藏
页码:501 / 515
页数:14
相关论文
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