Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization

In this paper, a systematic design approach based on noise optimization with power consumption minimization for operational transconductance amplifiers (OTAs) is presented. In this methodology, HSPICE and ant colony optimization (ACO) algorithm are used as simulation tool and optimization method, respectively. By re-writing the thermal noise, flicker noise, corner frequency and other specifications of the OTA based on the Gm/Id characteristic in all regions of transistor operation, noise optimization beside the power minimization is achieved in a reasonable simulation time. In this approach, ACO is applied in order to optimize the design variables, aim at minimizing the input referred noise and power consumption. The design methodology is successfully used for systematic design and optimization of a CMOS Miller folded cascade amplifier using 0.18 µm CMOS technology in the three regions of amplifier operation. Simulation results confirm the accuracy of the theoretical analysis in the presented design methodology.