A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor

被引:0
作者
Huaizhi Luo
Yan Li
Fei Zhao
Xi Zhang
Shengkai Wang
Wenjun Xiong
Xiaotong Mao
Yongliang Li
机构
[1] Beijing Information Science and Technology University,School of Applied Science
[2] Institute of Microelectronics of the Chinese Academy of Sciences,Integrated Circuit Advanced Process Center
[3] Institute of Microelectronics of the Chinese Academy of Sciences,High
来源
Silicon | 2024年 / 16卷
关键词
SiO; interfacial layer; I/O transistor; GAA; Low-temperature; RTO;
D O I
暂无
中图分类号
学科分类号
摘要
In this paper, a low-temperature SiO2 interfacial layer preparation using rapid thermal oxidation (RTO) process for gate-all-around (GAA) nanosheet (NS) based input-output (I/O) transistor is explored in detail. After preparing high-quality thick SiO2 IL at 600℃, its MOS capacitor with W/TiN/HfO2/SiO2/Si substrate structure achieves well behaved multi-frequency capacitance-voltage characteristics, low leakage current, low interfacial trap density (Dit), and excellent time-dependent dielectric breakdown. For instance, its gate leakage under flatband voltage (Vfb) -1 V is only 2.48 × 10–9 A/cm2, its minimum Dit reaches 5.1 × 1010 eV−1 cm−2, and its ten-year lifetime effective voltage can reach 3.62 V at a failure rate of 0.01%. Moreover, a GAA NS based I/O device with a healthy gate stack is successfully prepared using this low-temperature SiO2 interfacial layer and its gate leakage is below 1 × 10–13 A, approaching the detection limit. These above results indicate that this low-temperature RTO-grown SiO2 IL has excellent quality and can meet the requirements of GAA NSs I/O transistors.
引用
收藏
页码:1619 / 1625
页数:6
相关论文
共 31 条
[1]  
Saleh R(2006)System-on-Chip: reuse and integration Proc IEEE 94 1050-1069
[2]  
Wilton S(2023)Stacked SiGe/Si I/O FinFET device preparation in a vertically stacked gate-all-around technology Mater Sci Semicond Process 164 601-2217
[3]  
Mirabbasi S(2000)Gate-induced-drain-leakage (GIDL) in CMOS enhanced by mechanical stress IEEE Trans Electron Devices 47 2214-712
[4]  
Hu A(2022)A novel charge pumping technique with gate-induced drain leakage current IEEE Trans Electron Devices 69 709-undefined
[5]  
Greenstreet M(2023)undefined IEEE Electron Device Lett 44 undefined-undefined
[6]  
Lemieux G(undefined)undefined undefined undefined undefined-undefined
[7]  
Pande PP(undefined)undefined undefined undefined undefined-undefined
[8]  
Grecu C(undefined)undefined undefined undefined undefined-undefined
[9]  
Ivanov A(undefined)undefined undefined undefined undefined-undefined
[10]  
Zhao F(undefined)undefined undefined undefined undefined-undefined