Patmos: a time-predictable microprocessor

被引:0
作者
Martin Schoeberl
Wolfgang Puffitsch
Stefan Hepp
Benedikt Huber
Daniel Prokesch
机构
[1] Technical University of Denmark,Department of Applied Mathematics and Computer Science
[2] Vienna University of Technology,Institute of Computer Languages
[3] Vienna University of Technology,Institute of Computer Engineering
来源
Real-Time Systems | 2018年 / 54卷
关键词
Real-time systems; Time-predictable architecture; Worst-case execution time;
D O I
暂无
中图分类号
学科分类号
摘要
Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.
引用
收藏
页码:389 / 423
页数:34
相关论文
共 99 条
[1]  
Axer P(2013)Building timing predictable embedded systems ACM Trans Embed Syst 13 82-34
[2]  
Ernst R(2013)Criticality: static profiling for real-time programs Real-Time Syst 50 1-50
[3]  
Falk H(2010)A compiler framework for the reduction of worst-case execution time Real-Time Syst 46 1-181
[4]  
Girault A(1999)Efficient and precise cache behavior prediction for real-time systems Real-Time Syst 17 131-490
[5]  
Grund D(1981)Trace scheduling: a technique for global microcode compaction IEEE Trans Comput C–30 478-70
[6]  
Guan N(1999)Bounding pipeline and instruction cache performance IEEE Trans. Comput 48 53-1054
[7]  
Jonsson B(2003)The influence of processor architecture on the design and results of WCET tools Proc IEEE 91 1038-248
[8]  
Marwedel P(1993)The superblock: an effective technique for vliw and superscalar compilation J Supercomput 7 229-492
[9]  
Reineke J(2016)Argo: a real-time network-on-chip architecture with an efficient GALS implementation IEEE Trans Very Large Scale Integr (VLSI) Syst 24 479-34
[10]  
Rochange C(2010)A real-time Java chip-multiprocessor ACM Trans. Embed. Comput. Syst. 10 1-286