New experiments on iterative synthesis of combinational circuits

被引：1

作者：

Bibilo P.N. ^{[1
]}

Romanov V.I. ^{[1
]}

机构：

[1] Joint Institute of Problems of Information Science, National Academy of Sciences of Belarus, Minsk

来源：

Russian Microelectronics | 2008年 / 37卷 / 03期

关键词：

Circuit complexity - Gate arrays - Iterative synthesis;

D O I：

10.1134/S1063739708030086

中图分类号：

学科分类号：

摘要：

A new strategy is presented for experiments on iterative synthesis of combinational circuits within a gate-array or an FPGA library. Results thus obtained are presented. Reductions in circuit complexity are achieved with each of the libraries. © 2008 MAIK Nauka.

引用

页码：201 / 212

页数：11

共 7 条

[1]

Nemudrov V., Martin G., Sistemy-na-kristalle. Proektirovanie i Razvitie, (2004)

[2]

Bibilo P.N., Sistemy Proektirovaniya integral'Nykh Skhem Na Osnove Yazyka VHDL. StateCAD, ModelSim, LeonardoSpectrum, (2005)

[3]

Bibilo P.N., Romanov V.I., Optimization of multilevel representations of boolean-function systems in logic-circuit redesign, Upr. Sist. Mash., 5, pp. 20-29, (2006)

[4]

Bibilo P.N., Kardash S.N., Romanov V.I., SiVer: A Software System for Combinational-Circuit Synthesis and Verification, Informatika, 4, pp. 79-87, (2006)

[5]

Bibilo P.N., Sintez Logicheskikh Skhem S ispol'Zovaniem Yazyka VHDL, (2002)

[6]

Kuzelin O.M., Knyshev D.A., Zotov Yu.V., Sovremennye Semeistva PLIS Firmy Xilinx. Spravochnoe Posobie, (2004)

[7]

Toropov N.R., DNF Minimization of Boolean Functions, Logicheskoe Proektirovanie, pp. 4-19, (1999)

← 1 →