3-D neural mapper for LDPC sum-product decoder

被引：0
作者：
Boiko Y. [1 ]
机构：
[1] Systems and Computer Engineering Department, Carleton University, Ottawa, ON K1S 5B6
来源：
Optical Memory and Neural Networks (Information Optics) | 2009年 / 18卷 / 02期
关键词：
LDPC decoder; Multilayer perceptron; Neural chip; On-chip training; Parity check; Sum-product algorithm;
D O I：
10.3103/S1060992X09020064
中图分类号：
学科分类号：
摘要：
Present article explores prospects for implementing 3D neural mapper suitable for operation in check nodes of sum-product decoding algorithm. Advantage of such mapper based on neural circuits is the allowed on-chip training, which offers potential for controlled accuracy of the mapping and eventually improved performance in the decoding (due to reduced bit error rate resulting from enhanced accuracy of the operations implemented by trained neural circuits). Simulation results presented in this report show feasibility of employing neural multilayer perceptron with practically acceptable number of hidden neurons to achieve high accuracy of the mapping for decoding based on sum-product algorithm. Specifically 7 hidden neurons are shown to attain accuracy better than 0.1%, which is suitable for implementation in decoding devices, such as low-density parity check (LDPC) decoders. © Allerton Press, Inc. 2009.
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页码：101 / 107
页数：6
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