A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.