Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications

This paper proposes a 10-bit 100 MS/s 20 MHz low power pipelined analog-to-digital converter (ADC) with switched capacitor based programmable gain amplifier (PGA) suitable for wireless receiver applications. In the proposed ADC the double loading problem caused in the first stage of 10-bit pipelined ADC is avoided. In order to minimize the power consumption, split-capacitor sharing correlated double sampling and op-amp sharing technique has been used. Using the technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined ADC. Switched capacitor topology based PGA occupies an area of 0.0031 mm2. Switched capacitor topology based PGA with the integration of 10-bit pipelined ADC consumes 25.54 mW of power at 100 MS/s from a 1.8 V power supply.