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Multi-TAP Controller Architecture for Digital System Chips
被引：0
作者：
Bart Vermeulen
Tom Waayers
Sjaak Bakker
机构：
[1] Philips Research Laboratories,
[2] Philips Semiconductors CTO/RTG,undefined
来源：
Journal of Electronic Testing
|
2003年
/
19卷
关键词：
system-chips;
IEEE-1149.1;
multi-TAP;
software-debug;
design-for-debug;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper describes an architecture for controlling multiple IEEE 1149.1 compliant TAP controllers on a single digital system chip. The key feature of this architecture is the compatibility with the IEEE 1149.1 standard, and existing debugger software. Results are presented, obtained from an experiment, in which the proposed architecture is mapped on an FPGA to control multiple existing designs with TAP controllers.
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页码：417 / 424
页数：7
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