Design Guidelines for the Noise Optimization of a 0.18 μm CMOS Low-Noise Amplifier

This paper presents the design considerations for the noise optimization of fully integrated tuned low-noise amplifiers (LNA) based on the four noise parameters and two-port noise theory. Specifically, this paper provides the design guidelines for a 0.18 μm CMOS tuned LNA. These guidelines give a useful indication to the design tradeoffs associated with noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology. As a case study, a 10 GHz LNA has been designed using 0.18 μm CMOS technology for a wireless LAN application. The amplifier has a 2.4 dB noise figure with a −13 dBm third-order input intercept point, while drawing 5 mW from a 1.8 V power supply. The results show that the proposed theoretical contours of constant noise figure which relate the gate overdrive voltage and power dissipation can accurately predict the noise performance of a 0.18 μm CMOS LNA design