Investigating the Source Stack Engineering Effect on the Drive Current of a Tunneling Field Effect Transistor

被引:0
作者
Behnaz Akbarnavaz Farkoush
Daryoosh Dideban
机构
[1] University of Kashan,Institute of Nanoscience and Nanotechnology
[2] University of Kashan,Department of Electrical and Computer Engineering
来源
Silicon | 2020年 / 12卷
关键词
Tunnel field effect transistor (TFET); Source engineering; Leakage current; Band to band tunneling (BTBT);
D O I
暂无
中图分类号
学科分类号
摘要
In this Research, the Effect of Source Stack Engineering on the Drive Current of a Proposed Silicon on Insulator-Tunnel FET (SOI-TFET) Is Investigated. The Proposed TFET Scheme Is Similar to a Conventional TFET, but there Is a P+ Doping Stack above the Source Region. Our Simulation Results Reveals that the Presence of Source Stack Increases the Electric Field, Lowers Tunneling Width and Then Enhances Band to Band Tunneling Rate in the Tunneling Junction of the Device. It Is Demonstrated that when theSiO2 Lip Length above Source Region Sets to 4 Nm and Silicon Stack Height Is 7 Nm, the Highest Drive Current Can Be Achieved. Moreover, Ion/Ioff Ratio of More than 2*1011 with Negligible Leakage Current (<0.1 fA) in the Proposed Device Indicates that this TFET Is among Promising Candidates for Low Power and High Performance Applications
引用
收藏
页码:2733 / 2740
页数:7
相关论文
共 68 条
[11]  
Saremi M(2011)Ambipolarity factor of tunneling field-effect transistors (TFETs) JSTS: Journal of Semiconductor Technology and Science 11 272-4758
[12]  
Reddy GV(2017)A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance IEEE Trans Electron Devices 64 4752-1172
[13]  
Kumar MJ(2009)Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis Jpn J Appl Phys 48 1170-96
[14]  
Anvarifard MK(2014)In-built N+ pocket pnpn tunnel field-effect transistor IEEE Electron Device Lett 35 92-586
[15]  
Orouji AA(2012)Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing IEEE Trans Electron Devices 60 584-146
[16]  
Shahnazarisani H(2013)Junctionless tunnel field effect transistor IEEE Electron Device Lett 34 138-26
[17]  
Mohammadi S(2016)Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement Superlattice Microst 94 17-2319
[18]  
Anvarifard MK(2017)Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance Superlattice Microst 102 2317-295
[19]  
Orouji AA(2007)Tunnel field-effect transistor without gate-drain overlap Appl Phys Lett 91 288-3547
[20]  
Choi WY(2010)Hetero-gate-dielectric tunneling field-effect transistors IEEE Trans Electron Devices 57 3541-5812