Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm

被引:0
作者
J. Mitéran
J. Matas
E. Bourennane
M. Paindavoine
J. Dubois
机构
[1] Université de Bourgogne,Le2i (UMR CNRS 5158), Aile des Sciences de l'Ingénieur
[2] BP 47870,undefined
[3] Center for Machine Perception—CVUT,undefined
来源
EURASIP Journal on Advances in Signal Processing | / 2005卷
关键词
Adaboost; FPGA; classification; hardware; image segmentation;
D O I
暂无
中图分类号
学科分类号
摘要
We propose a method and a tool for automatic generation of hardware implementation of a decision rule based on the Adaboost algorithm. We review the principles of the classification method and we evaluate its hardware implementation cost in terms of FPGA's slice, using different weak classifiers based on the general concept of hyperrectangle. The main novelty of our approach is that the tool allows the user to find automatically an appropriate tradeoff between classification performances and hardware implementation cost, and that the generated architecture is optimized for each training process. We present results obtained using Gaussian distributions and examples from UCI databases. Finally, we present an example of industrial application of real-time textured image segmentation.
引用
收藏
相关论文
共 39 条
  • [31] Formulation, analysis, and hardware implementation of chaotic dynamics based algorithm for compression and feature recognition in digital images
    Glenn, Chance M.
    Mantha, Srikanth
    George, Sajin
    Atluri, Deepti
    Mondragon-Torres, Antonio F.
    IMAGE PROCESSING: ALGORITHMS AND SYSTEMS XI, 2013, 8655
  • [32] Hardware implementation of a novel water marking algorithm based on phase congruency and singular value decomposition technique
    Nayak, Manas Ranjan
    Bag, Joyashree
    Sarkar, Souvik
    Sarkar, Subir Kumar
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2017, 71 : 1 - 8
  • [33] Implementation of High Performance Hardware Architecture of Face Recognition Algorithm Based on Local Binary Pattern on FPGA
    Zhang, Yangjie
    Cao, Wei
    Wang, Lingli
    PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
  • [34] Temporal High-Pass Non-uniformity Correction algorithm based on Grayscale Mapping and Hardware Implementation
    Jin, Minglei
    Jin, Weiqi
    Li, Yiyang
    Li, Shuo
    2015 INTERNATIONAL CONFERENCE ON OPTICAL INSTRUMENTS AND TECHNOLOGY: OPTOELECTRONIC IMAGING AND PROCESSING TECHNOLOGY, 2015, 9622
  • [35] Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking
    Das, Subhajit
    Sunaniya, Arun Kumar
    Maity, Reshmi
    Maity, Niladri Pratap
    IEEE ACCESS, 2020, 8 : 69072 - 69095
  • [36] ATLAAS: an automatic decision tree-based learning algorithm for advanced image segmentation in positron emission tomography
    Berthon, Beatrice
    Marshall, Christopher
    Evans, Mererid
    Spezi, Emiliano
    PHYSICS IN MEDICINE AND BIOLOGY, 2016, 61 (13) : 4855 - 4869
  • [37] Ontology-Based Decision Support Tool for Automatic Sleep Staging Using Dual-Channel EEG Data
    Zhang, Bingtao
    Yang, Zhifei
    Cai, Hanshu
    Lian, Jing
    Chang, Wenwen
    Zhang, Zhonglin
    SYMMETRY-BASEL, 2020, 12 (11): : 1 - 18
  • [38] A novel algorithm and hardware implementation for correcting sensor non-uniformities in infrared focal plane array based staring system
    Kumar, Ajay
    Sarkar, S.
    Agarwal, R. P.
    INFRARED PHYSICS & TECHNOLOGY, 2007, 50 (01) : 9 - 13
  • [39] A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation
    Tan, Hai Jun
    Chan, Shing Chow
    Lin, Jian Qiang
    Sun, Xu
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (01) : 198 - 211