A 17 GHz direct digital synthesizer in a InP DHBT technology

被引:0
作者
Yi Zhang
Xiaopeng Li
Youtao Zhang
Min Zhang
Yufeng Guo
Hao Gao
机构
[1] Nanjing University of Posts and Telecommunications,National and Local Joint Engineering Laboratory of RF and Micro
[2] Southeast University,assembly Technology
[3] Nanjing Electronic Device Institute,State Key Laboratory of Millimeter Waves
[4] Eindhoven University of Technology,undefined
来源
Sādhanā | 2021年 / 46卷
关键词
DDS; InP DHBT; nonlinear DAC; phase accumulator; clock distribution;
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摘要
Direct digital synthesizer (DDS) is an essential part of the multi-band digital phased array radar system due to its broad frequency generation ability. In this paper, a 17 GHz 8-bit ROM-less DDS in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. The DDS adopts a sin-weighted nonlinear Digital-to-Analog Converter (DAC) to achieve phase-to-amplitude conversion. A simplified pipelined phase accumulator is applied, and its adder is designed according to the majority decision algorithm to reduce power consumption. The DDS is fabricated in an in-house 0.7 μm InP DHBT technology. The measured results demonstrate that the maximum input clock frequency is 17 GHz, and it can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps. The average Spurious-free dynamic range (SFDR) for the output signal of the DDS is − 18.1 dBc. The chip integrates about 1700 transistors, consumes 7.4 W, and has a Figure of merit (FOM) of 2.3 GHz/W.
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