Gate-All-Around MOSFET Built on Void Embedded Silicon on Insulator Substrate

被引：12

作者：

Liu, Qiang ^{[1
,2
]}

Mu, Zhiqiang ^{[1
,2
]}

Liu, Chenhe ^{[1
,2
]}

Zhao, Lantian ^{[1
,2
]}

Chen, Lingli ^{[1
,2
]}

Yang, Yumeng ^{[3
]}

Wei, Xing ^{[1
,2
]}

Yu, Wenjie ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China

[2] Univ Chinese Acad Sci, Coll Mat Sci & Optoelect Technol, Beijing 100049, Peoples R China

[3] ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai 201210, Peoples R China

来源：

IEEE ELECTRON DEVICE LETTERS | 2021年 / 42卷 / 05期

关键词：

Logic gates; Gallium arsenide; Silicon; Substrates; Silicon-on-insulator; Etching; MOSFET; Gate-all-around; void embedded silicon on insulator; suspended Si channels; subthreshold swing;

D O I：

10.1109/LED.2021.3066171

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel method for manufacturing gate-all-around metal-oxide-semiconductor field effect transistor (GAA MOSFET) based on void embedded silicon on insulator (VESOI) substrate is demonstrated in this work. VESOI with embedded submicron void chambers has been designed to fabricate suspended silicon channels by a one-step lithography and dry etching process. GAA MOSFET built on VESOI substrate exhibits excellent characteristics with subthreshold swing (SS) about 63mV/dec, ON/OFF ratio of 10(10), drain-induced barrier lowering (DIBL) less than 12mV/V and strong tolerance to back gate bias. This method shows significant advantages to fabricate suspended Si channels, and can be readily extended to other types of material systems for low-power and high-performance applications.

引用

页码：657 / 660

页数：4

共 17 条

[1]

[Anonymous], 2015, INT TECHN ROADM SEM

[2] Silicon carbide on insulator formation using the Smart Cut process [J].