Xtensa with user defined DSP coprocessor microarchitectures

被引：8

作者：

Ezer, G

机构：

来源：

2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ICCD.2000.878305

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the third generation configurable and extensible Xtensa(TM) processor with enhanced DSP functionality targeted to System-On-Chip (SOC) designs. Xtensa in processor family can be configured with an IEEE-compatible floating paint unit (FPU) and/or a powerful, energy efficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core.

引用

页码：335 / 342

页数：8