Low-power flip-flops with reliable clock gating

被引：15

作者：

Strollo, AGM ^{[1
]}

Napoli, E ^{[1
]}

De Caro, D ^{[1
]}

机构：

[1] Univ Naples Federico II, Dept Elect & Telecommun Engn, I-80125 Naples, Italy

来源：

MICROELECTRONICS JOURNAL | 2001年 / 32卷 / 01期

关键词：

CMOS digital integrated circuits; flip-flops; low-power circuits; transition probability;

D O I：

10.1016/S0026-2692(00)00072-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents two gated flip-flops aimed at low-power applications. The proposed hip-hops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter and an audio sampler register are presented as examples of low-power applications. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：21 / 28

页数：8

共 17 条

[1] Precomputation-based sequential logic optimization for low power [J].

Alidina, Mazhar ;

Monteiro, Jose ;

Devadas, Srinivas ;

Ghosh, Abhijit ;

Papaefthymiou, Marios .

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, 2 (04) :426-436

[2] Automatic synthesis of low-power gated-clock finite-state machines [J].

Benini, L ;

DeMicheli, G .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (06) :630-643

[3] LOW-POWER CMOS DIGITAL DESIGN [J].

CHANDRAKASAN, AP ;

SHENG, S ;

BRODERSEN, RW .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484

[4]

DOBBERPUHL D, 1996, P INT S LOW POW EL D, P11

[5] Reducing switching activity on datapath buses with control-signal gating [J].

Kapadia, H ;

Benini, L ;

De Micheli, G .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (03) :405-414

[6] A reduced clock-swing flip-flop (RCSFF) for 63% power reduction [J].

Kawaguchi, H ;

Sakurai, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (05) :807-811

[7] Individual flip-flops with gated clocks for low power datapaths [J].

Lang, T ;

Musoll, E ;

Cortadella, J .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1997, 44 (06) :507-516

[8] A low-power asynchronous data-path for a FIR filter bank [J].

Nielsen, LS ;

Sparso, J .

SECOND INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1996, :197-207

[9] A data-transition look-ahead DFF circuit for statistical reduction in power consumption [J].

Nogawa, M ;

Ohtomo, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (05) :702-706

[10] Automatic insertion of gated clocks at register transfer level [J].

Raghavan, N ;

Akella, V ;

Bakshi, S .

TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1999, :48-54

← 1 2 →