Scalable FFT Architecture vs. Multiple Pipeline FFT Architectures-Hardware Implementation and Cost

被引：1

作者：

Suleiman, Adnan ^{[1
]}

Hussein, Adel ^{[1
]}

Bataineh, Khaldoun ^{[1
]}

Akopian, David ^{[1
]}

机构：

[1] Univ Texas San Antonio, San Antonio, TX 78249 USA

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS (SMC 2009), VOLS 1-9 | 2009年

关键词：

Scalable; Architecture; FFT; 45nm technology; FIFO;

D O I：

10.1109/ICSMC.2009.5346639

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). Hardware comparison to other existing pipeline architecture presented based on implementation of 1024-point FFT with 4 processing elements using 45nm process technology. The proposed architecture is most suitable for handheld and portable multimedia applications

引用

页码：3792 / 3796

页数：5

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