Optimal Topologies for Cascaded Sub-Multilevel Converters

被引:85
作者
Babaei, Ebrahim [1 ]
机构
[1] Univ Tabriz, Fac Elect & Comp Engn, Tabriz, Iran
关键词
Bidirectional switch; Cascaded multilevel converter; Lagrange multiplier; Multilevel converter; Sub-multilevel converter; INVERTERS; ALGORITHM;
D O I
10.6113/JPE.2010.10.3.251
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The general function of a multilevel converter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new topology is recommended in [1], which benefits from a series connection of sub-multilevel converters. In the procedure described in this reference, despite all the advantages, it is not possible to produce all the steps (odd and even) in the output. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for this topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation and experimental results for a 49-level converter with a maximum output voltage of 200V are presented.
引用
收藏
页码:251 / 261
页数:11
相关论文
共 27 条
[1]   A novel switching algorithm to balance conduction losses in power semiconductor devices of full-bridge inverters [J].
Aghdam, M. G. Hosseini ;
Fathi, S. H. ;
Gharehpetian, G. B. .
EUROPEAN TRANSACTIONS ON ELECTRICAL POWER, 2008, 18 (07) :694-708
[2]  
[Anonymous], P IAS ANN M CINC OH
[3]   Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology [J].
Babaei, E. ;
Hosseini, S. H. ;
Gharehpetian, G. B. ;
Haque, M. Tarafdar ;
Sabahi, M. .
ELECTRIC POWER SYSTEMS RESEARCH, 2007, 77 (08) :1073-1085
[4]  
BABAEI E, 2005, P 8 INT C EL MACH SY, V2, P1278
[5]   A Cascade Multilevel Converter Topology With Reduced Number of Switches [J].
Babaei, Ebrahim .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2008, 23 (06) :2657-2664
[6]  
Baiju M. R., 2003, EPE Journal, V13, P29
[7]  
Baker I.R.H., 1975, U.S. Patent, Patent No. [3,867,643, 3867643]
[8]  
Baker R. H., 1980, US Patent, Patent No. [04-203-151, 04203151]
[9]   Control of cascaded multilevel inverters [J].
Corzine, KA ;
Wielebski, MW ;
Peng, FZ ;
Wang, J .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2004, 19 (03) :732-738
[10]  
Du Z, 2006, APPL POWER ELECT CO, P426