Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

被引：2

作者：

Hu, Chih-Chan ^{[1
]}

Chau, Yuan-Fong Chou ^{[2
]}

Lim, Chee Ming ^{[2
]}

Tan, Kuang-Hsiung ^{[3
]}

机构：

[1] Natl Chung Shan Inst Sci & Technol, Syst Mfg Ctr, Sanxia 23742, Taiwan

[2] Univ Brunei Darussalam, Ctr Adv Mat & Energy Sci, BE-1410 Gadong, Brunei

[3] Natl Def Univ, Chung Cheng Inst Technol, Dept Elect & Elect Engn, Taoyuan 335, Taiwan

来源：

MICROELECTRONICS RELIABILITY | 2016年 / 60卷

关键词：

Low-frequency noise; CMOS; MOSFET; Flicker noise; Random telegraph signals; PHASE-NOISE; FLICKER NOISE; FLUCTUATIONS;

D O I：

10.1016/j.microrel.2016.02.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We analyzed the noise characteristics of 0.18 mu m and 0.35 mu m nMOSFETs with a gate area of 1.1 mu m(2) in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 mu m gate-length nMOSFET possesses lower 1/f component than the 0.18 mu m one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 035 mu m gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width. (C) 2016 Elsevier Ltd. All rights reserved.

引用

页码：10 / 15

页数：6

共 13 条

[1] Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics
Giusi, G
Crupi, F
Pace, C
Ciofi, C
Groeseneken, G
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) : 823 - 828
[2] Low-Frequency Noise in a 0.18 μm Mixed-Mode CMOS Technology at Low Temperature
Martin, P.
Cavelier, M.
Ghibaudo, G.
NOISE AND FLUCTUATIONS, 2009, 1129 : 317 - +
[3] A 0.18 μm dual-gate CMOS model for the design of 2.4 GHz low noise amplifier
Liang, Kung-Hao
Chan, Yi-Jen
2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2006, : 353 - +
[4] A 0.18 μm dual-gate CMOS model for the design of 2.4 GHz low noise amplifier
Liang, Kung-Hao
Chan, Yi-Jen
2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, 2006, : 313 - 316
[5] Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO2/HfO2 Gate Dielectrics
Gorchichko, Mariia
Cao, Yanrong
Zhang, En Xia
Yan, Dawei
Gong, Huiqi
Zhao, Simeng E.
Wang, Pan
Jiang, Rong
Liang, Chundong
Fleetwood, Daniel M.
Schrimpf, Ronald D.
Reed, Robert A.
Linten, Dimitri
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2020, 67 (01) : 245 - 252
[6] Low-Frequency Noise Analysis in HfO2/SiON Gate Stack nMOSFETs with Different Interfacial Layer Thickness
Choi, Do-Young
Baek, Rock-Hyun
Jeong, Yoon-Ha
PHYSICS OF SEMICONDUCTORS: 30TH INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, 2011, 1399
[7] Low frequency noise and reliability properties of 0.12μm CMOS devices with Ta2O5 as gate dielectrics
Fadlallah, M
Szewczyk, A
Giannakopoulos, C
Cretu, B
Monsieur, F
Devoivre, T
Jomaah, J
Ghibaudo, G
MICROELECTRONICS RELIABILITY, 2001, 41 (9-10) : 1361 - 1366
[8] Low-frequency noise Behavior of SiO2-HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness
Simoen, E
Mercha, A
Pantisano, L
Claeys, C
Young, E
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (05) : 780 - 784
[9] A study of electrical characteristics improvements in sub-0.1 μm gate length MOSFETs by low temperature operation
Tsuno, M
Yokoyama, S
Shibahara, K
IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (12) : 1913 - 1917
[10] A 2-10 GHz Ultra-Wideband Common-Gate Low Noise Amplifier using Body Bias Technique in 0.18 μm CMOS
Mubashir, Syed
Singh, Vikram
PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC), 2017, : 541 - 545

← 1 2 →