Phase-noise driven system design of fractional-N frequency synthesizers and validation with measured results

Phase noise has been a primary issue in the design of frequency synthesizers. The system level noise analysis of a fractional-N (frac-N) PLL is presented to enable the circuit design of a 5-Mbps GMSK modulated data transmitter in the 900 MHz ISM band. A mathematical model describes the noise contributions due to the Charge Pump (CP), the phase frequency detector (PFD), the loop filter, the VCO, and the delta-sigma modulator The model takes into account the effects of Delta Sigma modulated CP pulse-widths on its thermal and flicker noise. The Delta Sigma sequence noise caused by static CP current mismatch, CP dynamic mismatch and PFD reset delay mismatch is taken into consideration in the noise analysis. Relying on a combined time-domain and frequency-domain noise analysis, the behavioral model provides fast and accurate phase noise estimation at the system level. This analysis enables the designer to determine the dominant contributors to the in-band and out-of-band phase noise simplifying the transistor level design of frac-N synthesizers. Measured results of a MASH-12 frac-N synthesizer designed in 1.8V TSMC 0.18 mu m Mixed Signal/RF process correlate well with behavioral noise model predictions. The proposed system noise analysis methodology has general applicability to frac-N PLL design.