Realization of an efficient VLSI architecture for discrete wavelet transform in real time image compression

被引：0
|
作者：
Hashad, AI [1 ]
Shehata, KA [1 ]
Gasser, SM [1 ]
机构：
[1] Arab Acad Sci Technol & Maritime Transport, Dept Elect & Commun, Cairo, Egypt
来源：
ICEEC'04: 2004 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/ICEEC.2004.1374566
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The discrete wavelet transforms is used as a forward transform in the JPEG2000 standard for still image compression. An efficient VLSI architecture is presented and its performance is evaluated and compared to the previously proposed architectures. This architecture is functionally simulated and synthesized on two different types of FPGA chips, the design statistics and dynamic performance (maximum switching frequency) turned out to be practically feasible.
引用
收藏
页码：673 / 676
页数：4
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