Transparent dual-gate InGaZnO thin film transistors: OR gate operation

Transparent dual-gate (DG) InGaZnO4 thin film transistors for OR logic operation were fabricated on a glass substrate. A 100-nm-thick SiO2 layer used as both top and bottom gate dielectrics was deposited by plasma enhance chemical vapor deposition at 200 degrees C. Compared to bottom gate, top gate thin film transistors (TFTs) exhibited better device performance with higher saturation mobility, drain current on-to-off ratio, lower threshold voltage, and subthreshold gate-voltage swing. This improved performance was mainly attributed to low process-induced damage or low parasitic capacitance between gate and source/drain and low parasitic resistance between channel and source/drain in top-contact TFT configuration (coplanar type). DG-mode TFTs showed saturation mobility of similar to 16.9 cm(2) V-1 s(-1), drain current on-to-off ratio of similar to 1 X 10(6), subthreshold gate-voltage swing of similar to 0.33 V decade(-1), and threshold voltage of similar to 1.25 V. The results demonstrate that DG InGaZnO4 TFTs are effective in improving the device performance because the channel layer is modulated independently by a top or, bottom gate signal and are well suited for OR gate operation. (C) 2009 American Vacuum Society. [DOI:10.1116/1.3196787]