A 1.5-dB Insertion Loss, 34-dBm P1dB Power Modulator with 46% Fractional Bandwidth in 45-nm CMOS SOI

被引：0

作者：

Hill, Cameron ^{[1
]}

Hamza, Ahmed ^{[1
]}

AlShammary, Hussam ^{[1
]}

Buckwalter, James F. ^{[1
]}

机构：

[1] Univ Calif Santa Barbara, Santa Barbara, CA 93106 USA

来源：

2019 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS) | 2019年

关键词：

SOI CMOS; RF Switch; Phase-shifter; High Power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work reports a high-power modulator implemented in 45-nm CMOS SOI for signal processing after the power amplifier. Two stacked switch variations, a 12 stack and 8 stack, were designed in 45-nm SOI CMOS and tested for trade-offs in insertion loss and power handling. These switches use a novel tapering technique to significantly improve switch linearity. The modulators have P-1dB values between 34 dBm and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1 GHz carrier. The IIP3 is between 46 dBm and 61 dBm.

引用

页码：243 / 246

页数：4

共 33 条

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