An FPGA interpolation processor for soft-decision reed-solomon decoding

被引：8

作者：

Gross, WJ ^{[1
]}

Kschischang, FR ^{[1
]}

Gulak, PG ^{[1
]}

机构：

[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 2A7, Canada

来源：

12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FCCM.2004.16

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision Reed-Solomon decoding algorithm. The key feature is the embedding of both a binary tree and a linear array into a two-dimensional array processor enabling fast polynomial evaluation operations. An FPGA interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mbps.

引用

页码：310 / 311

页数：2