High-throughput memory-based architecture for DHT using a new convolutional formulation

被引:20
作者
Meher, Pramod K. [1 ]
Patra, Jagdish C.
Swamy, M. N. S.
机构
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
[2] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ H3G 1M8, Canada
关键词
discrete Hartley transform (DHT); systolic array; VLSI;
D O I
10.1109/TCSII.2007.894407
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new formulation is presented for the computation of an N-point discrete Hartley transform (DHT) from two pairs of [(N/2 - 1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures.
引用
收藏
页码:606 / 610
页数:5
相关论文
共 13 条
[1]  
Amira A, 2003, 2003 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL 2, PROCEEDINGS, P567
[2]   A split vector-radix algorithm for the 3-D discrete Hartley transform [J].
Bouguezel, Saad ;
Ahmad, M. Omair ;
Swamy, M. N. S. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (09) :1966-1976
[3]   DISCRETE HARTLEY TRANSFORM [J].
BRACEWELL, RN .
JOURNAL OF THE OPTICAL SOCIETY OF AMERICA, 1983, 73 (12) :1832-1835
[4]  
Chiper DF, 2005, ISSCS 2005: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, P167
[5]  
Fang WH, 1999, IEICE T FUND ELECTR, VE82A, P2219
[6]  
Guo J. I., 2000, Pattern Recognition and Image Analysis, V10, P368
[7]  
GUO JI, 1994, P IEEE C AC SPEECH S, V2, P501
[8]   ON THE DESIGN AUTOMATION OF THE MEMORY-BASED VLSI ARCHITECTURES FOR FIR FILTERS [J].
LEE, HR ;
JEN, CW ;
LIU, CM .
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1993, 39 (03) :619-629
[9]   EFFICIENT SYSTOLIC SOLUTION FOR A NEW PRIME FACTOR DISCRETE HARTLEY TRANSFORM ALGORITHM [J].
MEHER, PK ;
SATAPATHY, JK ;
PANDA, G .
IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1993, 140 (02) :135-139
[10]   UNCONSTRAINED HARTLEY DOMAIN LEAST MEAN-SQUARE ADAPTIVE FILTER [J].
MEHER, PK ;
PANDA, G .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1993, 40 (09) :582-585