TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0

被引:12
作者
Greaves, David [1 ]
Yasin, Mehboob [2 ]
机构
[1] Univ Cambridge, Comp Lab, Cambridge CB3 0FD, England
[2] King Faisal Univ, Comp Lab, Al Ahasa, Saudi Arabia
来源
MODELS, METHODS, AND TOOLS FOR COMPLEX CHIP DESIGN: SELECTED CONTRIBUTIONS FROM FDL 2012 | 2014年 / 265卷
关键词
DESIGN;
D O I
10.1007/978-3-319-01418-0_4
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We report on a SystemC add-on library which extends every SystemC module with non-functional data regarding power consumption and physical layout and which accumulates and estimates dynamic energy usage. It supports both phase/mode power modelling and energy-per-transaction logging for TLM (transactional-level modelling). Wiring energy is computed by counting bit-level activity within the TLM generic payload. Each leaf component can also register its physical dimensions to facilitate a wire length estimator that traverses the SystemC model hierarchy using either full placement or Rent's rule estimators. It also supports dynamic voltage islands and inter-chip wiring, where each transaction can consume energy according to the current supply voltage of the relevant islands and the nature of the interconnect. We report on basic performance from some SPLASH-2 benchmarks running on a modelled OpenRISC quad-core platform.
引用
收藏
页码:53 / 68
页数:16
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