A Mixed-Mode Neuron with On-Chip Tunability for Generic Use in Memristive Neuromorphic Systems

被引:4
|
作者
Sayyaparaju, Sagarvarma [1 ]
Weiss, Ryan [1 ]
Rose, Garrett S. [1 ]
机构
[1] Univ Tennessee, Dept Elect Engn & Comp Sci, Knoxville, TN 37996 USA
关键词
SYNAPSE; NETWORK;
D O I
10.1109/ISVLSI.2018.00086
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Memristors are two-terminal nanoscale devices that provide an efficient way of implementing non-volatile synaptic weights. Realization of large scale memristive neuromorphic systems is reliant on rigorous custom design of neurons that are optimized to accumulate and spike according to the conductance range of the specific memristor employed. However, each new custom neuron design entails meticulous design effort and exorbitant re-fabrication costs. Circumventing this issue, we propose a generic mixed-mode neuron suitable for use across multiple memristor device implementations. The proposed neuron's accumulation rate is tunable with a set of reference voltages that are provided externally, through the pins on the chip. Hence, the proposed neuron exhibits on-chip accumulation rate tunability and is independent of the specific memristor chosen. This is exemplified in this paper by considering a small scale shape recognition network that employs these neurons. Moreover, the proposed neuron is shown to consume less energy per spike in comparison to a traditional integrate and fire neuron built in the same technology while occupying comparable silicon (layout) area. Lastly, the proposed neuron is shown to reduce the overall pin count for large scale memristive neuromorphic systems.
引用
收藏
页码:441 / 446
页数:6
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