High-level test synthesis based on controller redefinition

被引：1

作者：

Fernandez, V ^{[1
]}

Sanchez, P ^{[1
]}

机构：

[1] Univ Cantabria, TEISA, Microelect Engn Grp, E-39005 Santander, Spain

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 19期

关键词：

design for testability; circuit CAD;

D O I：

10.1049/el:19971114

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel approach is proposed for the high-level synthesis of data-dominated circuits. The functionality of the controller is redefined in order to improve the testability of the final circuit. The data path is left untouched. Test results are obtained at gate-level, after the RT synthesis process, with a sequential test generation package, HITEC.

引用

页码：1596 / 1597

页数：2