Testing 3D Chips Containing Through-Silicon Vias

被引：0

作者：

Marinissen, Erik Jan ^{[1
]}

Zorian, Yervant ^{[2
]}

机构：

[1] IMEC VZW, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Virage Log, Fremont, CA 94538 USA

来源：

ITC: 2009 INTERNATIONAL TEST CONFERENCE | 2009年

关键词：

3-DIMENSIONAL INTEGRATED-CIRCUITS; DESIGN; PERFORMANCE; BIST;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

引用

页码：569 / +

页数：3

共 46 条

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