Design of totally self-checking code-disjoint synchronous sequential circuits

Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. In this paper, we present a new approach to designing totally self-checking (TSC) code-disjoint (CD) SMs protected against errors using unordered codes. It is assumed that D flip-flops are used as the memory elements and that the circuit should be TSC for all single stuck-at faults (except for the faults on the clock lines), and CD for all input unidirectional errors. The initial 2-level AND-OR equations (with all products shared) are checked for self-testing by verifying some algebraic conditions. All stuck-at-1 faults which cannot be detected during normal functioning are identified. Then, the circuit is modified to the AND-AND-OR circuit with generally higher fault coverage. The resulting circuit is minimized using the well known SIS CAD tools. The whole design process has been automated by using the newely developed software tools that accept the BLIF representation of a SM and are compatible with the SIS tools. Many benchmark SMs can now be implemented as TSC with 100% fault coverage.