Development of signal detection & storage system with time-interleaved technology based on multi-SHARC DSP and PCI bus

被引:0
作者
Qi, XH [1 ]
Lin, ML [1 ]
Song, LZ [1 ]
Qiao, XL [1 ]
机构
[1] Harbin Inst Technol, Dept Informat, WeiHai 264209, Peoples R China
来源
PROCEEDINGS OF THE THIRD INTERNATIONAL SYMPOSIUM ON INSTRUMENTATION SCIENCE AND TECHNOLOGY, VOL 1 | 2004年
关键词
time-interleaved; high-speed sampling; real-time storage; SHARC; PCI; SCSI;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
During a signal detection, 16 times 8192 points complex FFT operation and signal detection & system control must be finished within 50 ms, at the same time, 4 channels video sampling data and a channel AGC sampling data must be stored under 20A4Hz sampling rate in real-time for a long time. For this, a scheme of high-speed signal synchronization sampling & storage, real-time signal detection system based on PCI bus is introduced, in which time-interleaved technology, 3 chips ADSP-21060 SHARC parallel signal processor, FLEX10K30 FPGA and SCSI hard disc are used. 4 channel, 8bit, 2KHzsimilar to33MHz programmable sampling rate and I channel, 12bit, 2KHzsimilar to33MHz programmable sampling rate are finished. The on-board data storage capability is 512 Mbytes. 3 chips ADSP-21060 SHARC parallel signal processor constitutes the signal process group with share bus mode. One is in charge of control and signal detection, the others are in charge of 8192 points complex FFT operation. The style of memory is SDRAM. PCI bus controller and SDRAM controller are implemented through FPGA with VHDL program. The experiment results indicate that the 66MHz sampling rate in 2 channel or 132MHz sampling rate in I channel based on time-interleaved technology is realized. 4 channels high-speed data storage is finished and the data storage time is determined by the capability of the hard disc. All the specifications are met.
引用
收藏
页码:1191 / 1195
页数:5
相关论文
共 6 条
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