Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier

被引:2
作者
Xiao, Hao [1 ]
Liu, Yuxuan [1 ]
Li, Zhenmin [1 ]
Liu, Guangzhu [1 ]
机构
[1] Hefei Univ Technol, Sch Microelect, Hefei 230601, Peoples R China
来源
IEICE ELECTRONICS EXPRESS | 2021年 / 18卷 / 10期
基金
中国国家自然科学基金;
关键词
modular multiplication; high throughput; ultra-high radix; FPGA IMPLEMENTATION; PROCESSOR; AREA;
D O I
10.1587/elex.18.20210135
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an algorithm-hardware co-design of ultrahigh radix modular multiplier for high throughput modular multiplication. First, to speed up the modular multiplication, we exploit an ultra-high radix interleaved modular multiplication algorithm with a novel segmented reduction method, which reduces the number of iterations and pre-computations. Then, to further improve the throughput of the modular multiplication, we design a highly parallel modular multiplier architecture. Finally, we implement and verify the modular multiplier using the Xilinx Virtex-7 FPGA. Experimental results show it can perform a 256-bit modular multiplication in 0.56 mu s with the throughput rate of up to 4999.7 Mbps.
引用
收藏
页数:6
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