Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier

被引：2

作者：

Xiao, Hao ^{[1
]}

Liu, Yuxuan ^{[1
]}

Li, Zhenmin ^{[1
]}

Liu, Guangzhu ^{[1
]}

机构：

[1] Hefei Univ Technol, Sch Microelect, Hefei 230601, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2021年 / 18卷 / 10期

基金：

中国国家自然科学基金;

关键词：

modular multiplication; high throughput; ultra-high radix; FPGA IMPLEMENTATION; PROCESSOR; AREA;

D O I：

10.1587/elex.18.20210135

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an algorithm-hardware co-design of ultrahigh radix modular multiplier for high throughput modular multiplication. First, to speed up the modular multiplication, we exploit an ultra-high radix interleaved modular multiplication algorithm with a novel segmented reduction method, which reduces the number of iterations and pre-computations. Then, to further improve the throughput of the modular multiplication, we design a highly parallel modular multiplier architecture. Finally, we implement and verify the modular multiplier using the Xilinx Virtex-7 FPGA. Experimental results show it can perform a 256-bit modular multiplication in 0.56 mu s with the throughput rate of up to 4999.7 Mbps.

引用

页数：6

共 30 条

[1] Very efficient point multiplication on Koblitz curves [J].

Al-Somani, Turki F. .

IEICE ELECTRONICS EXPRESS, 2016, 13 (09)

[2]

BLAKLEY GR, 1983, IEEE T COMPUT, V32, P497, DOI 10.1109/TC.1983.1676262

[3] Area and time efficient modular multiplication of large integers [J].

Bunimov, V ;

Schimmler, M .

IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, PROCEEDINGS, 2003, :400-409

[4] Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields [J].

Choi, Piljoo ;

Lee, Mun-Kyu ;

Kim, Ji-Hoon ;

Kim, Dong Kyue .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (11) :1703-1707

[5] High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication [J].

Ding, Jinnan ;

Li, Shuguo ;

Gu, Zhen .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (03) :1003-1016

[6] A reconfigurable high-speed ECC processor over NIST primes [J].

Ding, Jinnan ;

Li, Shuguo .

2017 16TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS / 11TH IEEE INTERNATIONAL CONFERENCE ON BIG DATA SCIENCE AND ENGINEERING / 14TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS, 2017, :1064-1069

[7] Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs [J].

Gallin, Gabriel ;

Tisserand, Arnaud .

IEEE TRANSACTIONS ON COMPUTERS, 2019, 68 (11) :1612-1622

[8] Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit [J].

Ghosh, Santosh ;

Mukhopadhyay, Debdeep ;

Roychowdhury, Dipanwita .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (08) :1798-1812

[9] A high-performance elliptic curve cryptographic coprocessor with side channel analysis countermeasures for smart IC card [J].

Han, Xiaowei ;

Wang, Beibei ;

Wu, Liji ;

Wang, An .

IEICE ELECTRONICS EXPRESS, 2015, 12 (20)

[10] High-performance elliptic curve cryptography processor over NIST prime fields [J].

Hossain, Md Selim ;

Kong, Yinan ;

Saeedi, Ehsan ;

Vayalil, Niras C. .

IET COMPUTERS AND DIGITAL TECHNIQUES, 2017, 11 (01) :33-42

← 1 2 3 →