A 22.5-30.5GHz CMOS Power Amplifier Using Pole -tuning Technique for 5G Applications

A four-stage wideband power amplifier (PA) using pole-tuning technique is presented for 5G applications. By tuning the relative pole position of each stage at different frequencies, the PA achieves a flat gain response over a wide bandwidth. To avoid transistor breakdown and hot carrier effect, self-biased cascode amplifiers are implemented in the first two stages. Common source amplifiers are utilized to ensure high output power. The PA was designed and simulated based on a 0.13 um CMOS process. The post-simulation result exhibits a peak gain of 22.2 dB at 28 GHz with -3-dB bandwidth of 8 GHz. The saturated output power (P.() and output 1 dB compression point (Pima) are 11.6 dBm and 7.8 dBm, respectively. The peak power added efficiency (PAE) is 17.3% The power consumption is 76 mW.