Transistor mismatch in 32 nm high-k metal-gate process

被引：1

作者：

Yuan, X. ^{[1
]}

Shimizu, T. ^{[2
]}

Mahalingam, U. ^{[3
]}

Brown, J. S. ^{[1
]}

Habib, K. ^{[1
]}

Tekleab, D. G. ^{[1
]}

Su, T. -C. ^{[1
]}

Satadru, S. ^{[3
]}

Olsen, C. M. ^{[1
]}

Lee, H. ^{[4
]}

Pan, L. -H. ^{[1
]}

Hook, T. B. ^{[1
]}

Han, J. -P. ^{[5
]}

Park, J. -E. ^{[1
]}

Na, M. -H. ^{[1
]}

Rim, K. ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Hopewell Jct, NY 12533 USA

[2] NEC Elect, Hopewell Jct, NY 12533 USA

[3] Global Foundries, Hopewell Jct, NY 12533 USA

[4] Samsung Elect, Hopewell Jct, NY 12533 USA

[5] Infineon Technol N Amer, Hopewell Jct, NY 12533 USA

来源：

ELECTRONICS LETTERS | 2010年 / 46卷 / 10期

关键词：

D O I：

10.1049/el.2010.0343

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Transistor mismatch data and analysis from state-of-the-art high-k/metal-gate (HKMG) technology are presented. By normalising mismatch data against oxide thickness (T-INV), threshold voltage (V-TH), and effective work function, direct comparison of V-TH mismatch from various device types is made. It is quantitatively demonstrated that effective work function variation (EWFV) does not generate significant V-TH variability in the present HKMG technology.

引用

页码：708 / U66

页数：2

共 50 条

[1] Reliability Characterization of 32nm High-K and Metal-Gate Logic Transistor Technology
Pae, Sangwoo
Ashok, Ashwin
Choi, Jingyoo
Ghani, Tahir
He, Jun
Lee, Seok-hee
Lemay, Karen
Liu, Mark
Lu, Ryan
Packan, Paul
Parker, Chris
Purser, Richard
St Amour, Anthony
Woolery, Bruce
2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, : 287 - 292
[2] Process Technology - High-k Metal-Gate integration
Texas Instruments
Tech. Dig. Int. Electron Meet. IEDM, 2008,
[3] BTI reliability of 45 nm high-k plus metal-gate process technology
Pae, S.
Agostinelli, M.
Brazie, M.
Chau, R.
Dewey, G.
Ghani, T.
Hattendorf, M.
Hicks, J.
Kavalieros, J.
Kuhn, K.
Kuhn, M.
Maiz, J.
Metz, M.
Mistry, K.
Prasad, C.
Ramey, S.
Roskowski, A.
Sandford, J.
Thomas, C.
Thomas, J.
Wiegand, C.
Wiedemer, J.
2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 352 - +
[4] 32nm Gate-First High-k/Metal-Gate Technology for High Performance Low Power Applications
Diaz, C. H.
Goto, K.
Huang, H. T.
Yasuda, Yuri
Tsao, C. P.
Chu, T. T.
Lu, W. T.
Chang, Vincent
Hou, Y. T.
Chao, Y. S.
Hsu, P. F.
Chen, C. L.
Lin, K. C.
Ng, J. A.
Yang, W. C.
Chen, C. H.
Peng, Y. H.
Chen , C. J.
Chen, C. C.
Yu, M. H.
Yeh, L. Y.
You, K. S.
Chen, K. S.
Thei, K. B.
Lee, C. H.
Yang, S. H.
Cheng, J. Y.
Huang, K. T.
Liaw, J. J.
Ku, Y.
Jang, S. M.
Chuang, H.
Liang, M. S.
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 629 - 632
[5] NBTI reliability on high-k metal-gate SiGe transistor and circuit performances
Yuan, Jiann-Shiun
Yeh, Wen-Kuan
Chen, Shuyu
Hsu, Chia-Wei
MICROELECTRONICS RELIABILITY, 2011, 51 (05) : 914 - 918
[6] High Performance DDR Architecture in Intel® Core™ processors using 32nm CMOS High-K Metal-Gate Process
Mosalikanti, Praveen
Mozak, Chris
Kurd, Nasser
2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 154 - 157
[7] Mismatch in High-K Metal Gate Process Analog Design
Woo, A.
Eberhart, H.
Li, Y.
Ito, A.
2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
[8] Gate Dielectric TDDB Characterizations of Advanced High-K and Metal-Gate CMOS Logic Transistor Technology
Pae, S.
Prasad, C.
Ramey, S.
Thomas, J.
Rahman, A.
Lu, R.
Hicks, J.
Batzerl, S.
Zhaol, Q.
Hatfield, J.
Liu, M.
Parker, C.
Woolery, B.
2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
[9] Sub-1nm EOT scaling for high-k/metal-gate stacks
Heyns, M
Schram, T
Ragnarsson, LÅ
De Gendt, S
Kerber, A
SOLID STATE TECHNOLOGY, 2004, 47 (07) : 22 - +
[10] Statistical Process Modelling For 32nm High-K/Metal Gate PMOS Device
Maheran, Afifah A. H.
Faizah, Noor Z. A.
Menon, P. S.
Ahmad, I.
Apte, P. R.
Kalaivani, T.
Salehuddin, F.
2014 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS (ICSE), 2014, : 232 - 235

← 1 2 3 4 5 →