Area and delay optimized two step binary adder using carry substitution algorithm for FIR filter

Adders are used to design the basic building blocks of very large scale integrated systems. Most of the computer arithmetic applications need highest degree of accuracy with good performance. In this paper a new efficient two step binary adder using carry substitution algorithm is proposed and it is implemented in digital FIR filter for filtering process. This adder architecture is very simple and efficient. Here two logic blocks namely half adder and carry substitution algorithm logic blocks are used. In the first step, the inputs are given to half adder logic block to generate the partial sum and carry bits. In the second step, carry substitution algorithm is used to compare the sum and carry bits generated by the adder logic to produce accurate final result. Here, the carry bits are not propagated from LSB to MSB. To study the effectiveness of the proposed two step binary adder, its performance is compared with the other existing parallel adders, parallel-prefix adders and approximate adders. These adders are coded in Verilog HDL and implemented in Xilinx FPGA. Simulation results show that FIR filter with the proposed adder is three times faster than FIR filter with parallel and parallel-prefix adders and two times faster than the FIR filter using approximate adders. Also the area of proposed method is 50% less and area delay product is 60% less compared to other designed FIR digital filters.